Integrated chips comprise semiconductor devices that are disposed within a semiconductor substrate, and which are interconnected together by way of a plurality of back-end-of-the-line (BEOL) metal interconnect layers formed over the semiconductor substrate. The metal interconnect layers are conductive wires and vias that connect the semiconductor devices to one another and to the outside world (e.g., to pins of an integrated chip package). The metal interconnect layers are disposed within a dielectric material that is formed over the semiconductor substrate. The dielectric material has a low dielectric constant (k) that provides for structural support of a metal interconnect layer without allowing for electrical shorting between different features of the metal interconnect layer.